This invention relates, in general, to multiprocessor computing systems and, more particularly, to a multiprocessor computing system capable of operating in a uniprocessor mode as well as in a parallel processing mode.
Generally speaking, computer programs may be executed by computing systems in various modes. For instance, any of a single instruction stream single data stream (SISD) mode; a single instruction stream multiple data stream (SIMD) mode; a single program multiple data stream (SPMD) mode; or a multiple instruction stream multiple data stream (MIMD) mode may be used to execute a typical computer program.
In SISD mode, a computer program generates and executes a single instruction stream to produce a single data stream or result. This is commonly referred to as a classical uniprocessor mode of operation. In addition, operation in a SISD mode often occurs even in multiprocessor or parallel systems. This may occur due to programming techniques, algorithmic serialization, or legacy from past implementations.
In many multiple processor or multiprocessor systems, computer programs may be executed in SIMD mode. In this mode, several pieces of data are simultaneously processed by a single instruction. Thus, several processors or processing elements may operate on a same instruction but with separate data-streams. In the SPMD variant of this mode, each processor executes a same program, which is fetched independently, and operates on its own data stream. Operation in SPMD mode allows the various processors to be attached only to local memory and communicate results over a message passing fabric or network.
In other multiprocessor systems, programs may be executed in a MIMD mode where each processor operates independently not only on its own data streams, but also on its own instruction streams. Processing in this mode is facilitated by either shared storage or by passing messages between the processors.
Classical multiprocessors, or shared memory processors (SMPs), allow programs to be executed in either SISD or MIMD modes, and sometimes in SPMD mode. However, these machines suffer from memory contention constraints. Because of this, the granularity of parallelism is usually limited to a level at which it is beneficial to execute several program-managed threads or processes which communicate by sharing memory, or by passing internal messages.
As such, it is desirable to exploit a finer grain of parallelism where single threads use several processors for short-lived bursts of parallel processing in conjunction with periods of intervening serial processing which exploit the higher memory bandwidth and the larger cache space provided by multiple processors. To meet this end, it is necessary to provide a computing system capable of switching between the various desired modes of operation. In addition, it is desirable to provide a computing system capable of such versatile operation without significant delay or without explicit programming through, for example, the use of special switch instructions. Further, the provision of a higher memory bandwidth and larger, faster cache is also desirable to facilitate efficient operation in SISD mode.
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of a technique for operating a computing system which relies on joining and forking,registers. By doing so, the technique of the present invention advantageously allows the processors of a computing system to rapidly and efficiently switch between the generation of single instruction and data streams and the generation of multiple instruction and data streams. As a result, the computing system of the present invention is capable of switching between multiple modes of operation. In addition, a higher memory bandwidth and a larger, faster cache is provided through the partitioning of memory and the fetching and broadcasting of information by a processor local to a particular section.
In one embodiment of the invention, a method of operating a computing system, wherein the computing system includes a plurality of processors with each processor having at least one instruction register, is provided. The method includes operating the plurality of processors in a multiple instruction mode, wherein the instruction registers generate separate instruction streams; and joining the instruction registers to switch operation of the plurality of processors to a single instruction mode, wherein the instruction registers generate a single instruction stream.
In another embodiment of the invention, a system for operating a computing system, wherein the computing system includes a plurality of processors with each processor having at least one instruction register is provided. The system includes means for operating the plurality of processors in a multiple instruction mode, wherein the instruction registers generate separate instruction streams; and means for joining the instruction registers to switch operation of the plurality of processors to a single instruction mode, wherein the instruction registers generate a single instruction stream.
In yet another embodiment of the invention, an article of manufacture including a computer useable medium having computer readable program code means embodied therein for operating a computing system, wherein the computing system includes a plurality of processors with each processor having at least one instruction register is provided. The computer readable program code means in the article of manufacture includes computer readable program code means for operating the plurality of processors in a multiple instruction mode, wherein the instruction registers generate separate instruction streams; and computer readable program code means for joining said instruction registers to switch operation of the plurality of processors to a single instruction mode, wherein the instruction registers generate a single instruction stream.
In an enhanced embodiment of the present invention the computing system includes a plurality of memory units with each memory unit being local to one processor and being remote to the remaining processors. This embodiment further includes fetching, when in the single instruction mode, an instruction stored in a memory unit by one processor which is local to the memory unit and broadcasting the instruction to the remaining processors which are not local to the memory unit; and fetching and not broadcasting, when in the multiple instruction mode, an instruction by each processor from its local memory unit.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention.